TTEP Tutorials at ITC 2006 - Call for Participation

CALL FOR PARTICIPATION

Overview -- TTEP Tutorials at ITC 2006 -- TTTC Tutorials and Education Group

Overview

The Tutorials & Education Group of the IEEE Computer Society Test Technology Technical Council (TTTC) presents a comprehensive set of seventeen full-day tutorials on topics of current interest to test professionals and researchers at ITC Test Week 2006 in Santa Clara, California. All tutorials qualify for credit towards IEEE TTTC certification under the TTEP program. Eight tutorials will be held on Sunday, October 22nd, and nine on Monday, October 23rd. The titles of tutorials are listed below.

For more details and registration information on the 2006 ITC/TTEP tutorials see the ITC Test Week 2006 Advance Program and Registration on www.itctestweek.org.

Advance registration deadline is September 25. Admission for on-site registrants is subject to availability. For further information regarding TTEP annual tutorials program, please visit:

http://tab.computer.org/tttc/teg/ttep/

TTEP Tutorials at ITC 2006

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TUTORIALS 1 to 8 Sunday, Oct. 22, 8:30 a.m. - 4:30 p.m.
TUTORIAL 1	NEW INTRODUCTORY TUTORIAL
Semiconductor Test and DFT Fundamentals Presenters: G. Perry, W. Mann
TUTORIAL 2	UPDATED
Advanced Memory Testing Presenter: A. van de Goor
TUTORIAL 3	UPDATED
GHz Interconnects -- Electrical Aspects Presenter: S. Jain
TUTORIAL 4	NEW
Design for Testability for RF Circuits and Systems Presenters: M. Margala, S. Ozev
TUTORIAL 5	UPDATED
Test Strategies for System-in-Package Presenter: Y. Zorian
TUTORIAL 6	UPDATED
Understanding failure mechanisms and test methods in nanometer technologies Presenters: J. Segura, C. Hawkins
TUTORIAL 7	UPDATED
Scan-Based Debug and Diagnosis Presenters: G. Eide, A. Crouch
TUTORIAL 8	UPDATED
Designing Testable Multi-Board Systems Using 1149.1 Architectures Presenters: B. Bennetts, B. van Treuren
TUTORIALS 9 to 17 Monday, Oct. 23, 8:30 a.m. - 4:30 p.m.
TUTORIAL 9	NEW
Design for Manufacturability Presenters: Y. Zorian, J.-A. Carballo
TUTORIAL 10	NEW
Memory Test Challenges - A practical and implementation view of BIST and other DFT techniques Presenters: V. Jayaram, S. Lai
TUTORIAL 11	NEW
Digital Timing Measurements - From Scopes and Probes to Timing and Jitter Presenter: W. Maichen
TUTORIAL 12	UPDATED
Practices in Analog, Mixed-signal and RF Design for Test Presenters: S. Abdennadher, S. Shaikh
TUTORIAL 13	UPDATED
Statistical Methods for VLSI Test, Quality and Reliability Presenter: A. Singh
TUTORIAL 14	*NEW*
Soft Errors: Technology Trends, System Effects, and Protection Techniques Presenters: S. Mitra, P. Sanda, N. Seifert
TUTORIAL 15	NEW
Debugging Compression based Tests like EDT, OPMISR, X-DBIST, LBIST Presenter: N. Dakwala
TUTORIAL 16	UPDATED
Dealing with timing issues for sub-100n designs - from modeling to mass production Presenters: L.-C. Wang, M. Abadir
TUTORIAL 17	*UPDATED*
Wafer Probe Test Technology Presenter: W. Mann

TTTC Tutorials and Education Group

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Chair
Dimitris Gizopoulos
University of Piraeus

Vice Chair (Organization)
Anand Raghunathan
NEC Labs

Vice Chair (Program)
Kaushik Roy
Purdue University

Planning
V. Agrawal, Auburn University
G. Robinson

Communications
M. Hsiao, Virginia Tech.

Industry Relations
R. Aitken, ARM

Finance
M. Nicolaidis, iRoC Technologies

Initiatives – New Topics
B. Courtois, TIMA

Publicity
Y. Makris, Yale University
C. Metra, University of Bologna

Audio/Visual
S. Menon, Intel

Electronic Media
G. Xenoulis, U. of Piraeus

Organizing Liaisons
U. Arz, PTB
T. Aikyo, Fujitsu
V. Champac, INAOE
I. Ghosh, Fujitsu
J. Madsen, TU Denmark
J. Segura, U. Illes Balears

Program Committee
V.D. Agrawal, Auburn U.
T. Aikyo, Fujitsu
R. Aitken, ARM Physical IP
D. Appello, ST Microelectronics
U. Arz, PTB
S. Bhunia, Case West. U.
K. Butler, Texas Instruments
S. Chakravarty, Intel
V. Champac, INAOE
S. Davidson, Sun
A. Gattiker, IBM
P. Harrod, ARM
K. Hatayama, Renesas
D. Josephson, Intel
J. Madsen, Techn. U. Denmark
H. Manhaeve, Q-Star
T. McLaurin, ARM
A. Paschalis, U. of Athens
A. Raghunathan, NEC Labs
R. Raina, Freescale
G. Roberts, McGill U.
M. Slamani, IBM
B. West, Credence
D. Wheater, IBM

For more information, visit us on the web at: http://tab.computer.org/tttc/teg/ttep

The Test Technology Educational Program 2006 (TTEP 2006) is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC).